The present invention relates to semiconductor power devices that have a wide base transistor therein, and more particularly to an apparatus and method for reducing breakdown voltage sensitivity to temperature and rate of change of voltage (dV/dT) in a semiconductor power device that has a wide base transistor by increasing the current through the base relative to the current through the emitter, either by diverting current from the emitter to the base or by injecting current from the collector into the base.
Various types of semiconductor power devices include a wide base transistor, such as the MOS controlled thyristor (MCT) 10 illustrated in FIG. 1 and the insulated gate bipolar transistor (IGBT) 20 illustrated in FIG. 2 (gate turn-on devices and silicon controlled rectifiers are further examples). In such devices, the transistor 12, 22 has a wide voltage carrying layer (the wide base 14, 24). Four layer devices, such as the MCT 10, may also include an upper transistor 16 having layers common to those of the lower, wide base transistor 12 (e.g., the wide base 14 is also the collector of the upper transistor 16). A buffer layer 15 may be placed between the lower emitter-base junction J1 and the wide base layer 14 to improve lateral conductivity of leakage currents away from the middle of the device. A circuit diagram equivalent to the P-MCT illustrated in FIG. 1 (an MCT with a P-type wide base) is shown in FIG. 3.
The operation of semiconductor power devices is discussed in Semiconductor Power Devices by S. K. Ghandi, John Wiley & Sons, 1977. Briefly, and with further reference to FIGS. 1 and 3, an MCT is turned on by the on-FET when a small voltage of one polarity (e.g., -5 volts) is applied to the gate 18. The voltage starts a regenerative action that turns on both the upper and wide base transistors 12, 16 so that the MCT conducts. The MCT is turned off by the off-FET when a small voltage of the opposite polarity (e.g., +7 volts) is applied to the gate. When the MCT is being turned off, the gate voltage creates an electric field in the channel region 19 beneath the gate; that is, the electric charge on the gate 18 causes the semiconductor type of the channel region 19 beneath the gate to convert to the opposite semiconductor type, effectively shorting the emitter-base junction of the upper transistor 16. The channel is a conductive path around the emitter that turns off the upper transistor 16 and stops MCT conduction (the device is in a blocking condition). When the MCT is in the blocking condition the wide base transistor 14 is not being shorted like the upper transistor and is essentially free to operate if a current, such as a leakage current, is applied thereto.
One of the problems associated with the wide base transistors, more so with NPN transistors than PNP transistors, is that they appear to be very fragile when the device is operated at high voltages with low current levels. Specifically, the operation of the transistor with an inductive load may be accompanied by voltage excursions beyond BV.sub.CEO. With reference to FIG. 4 that illustrates the common emitter characteristics of a semiconductor power device, it may be seen that at extremely low current levels, the breakdown voltage rises to its upper limit of BV.sub.CBO. Once this voltage is exceeded, the current through the device increases, accompanied by an increase in current gain. As a result, the device voltage "snaps back" as illustrated by line portion AB. Operation under these conditions leads to device failure caused by lateral electrical instability.
The extremely low current levels that may cause such failure are associated with temperature induced leakage currents and/or dV/dT induced leakage currents that may be found in semiconductor power devices.
The inventors have determined that these induced leakage currents are the reason why semiconductor power devices do not achieve their experimentally determined breakdown voltage under actual operating conditions. For example, a P-MCT with an experimentally determined breakdown voltage of 1460 volts may have an actual breakdown voltage of only about 900 volts. With reference now to FIG. 5 (experimental results for a P-MCT under varying temperature and dV/dT conditions), it may be seen that as the temperature of the device increases, the breakdown voltage of the device decreases. Similarly as dV/dT increases at low temperature, the breakdown voltage decreases.
By way of explanation, and using the P-MCT as an example, when the P-MCT is in the blocking condition the electric charge on the gate forms an inversion channel 19 that shunts current flowing through the upper transistor 16, bypassing the upper emitter-base junction and preventing the device from latching on. The small cell sizes employed in the fabrication of MCTs ensure that the upper transistor 16 is well shorted even under large dV/dT conditions.
In contrast, the wide base transistor 12 of the P-MCT is not shorted, is in an open base state when in the blocking condition, and may have an open base current therein. If it is assumed that the upper transistor of the MCT is completely shunted by the off-FET and does not contribute any back injection, then the open base current equation for the wide base transistor is: ##EQU1## where M is the multiplication factor, .alpha..sub.O is the current gain, I.sub.CO is the open emitter leakage current, and C dV/dT is the capacitive current component.
Breakdown takes place when I.sub..alpha.k gets very large with small increases in voltage. This occurs in the open base situation when the effective multiplication defined below gets large. ##EQU2##
The variable M is a function of the doping profile, the applied voltage, and the carrier type initiating the ionization and may be calculated for a specific voltage using known techniques. The current gain, .alpha..sub.O, is a function of the wide base transistor 12 doping profile, base/collector voltage, transistor type, temperature, and the current level in the wide base transistor 12.
The dependence on current level can be significant. If current gain, .alpha..sub.O, is strongly dependent on current level at low current levels, as it is in the wide base NPN transistors of semiconductor power devices, then the .alpha..sub.O * M product will change as the current level through the device changes. When the change causes the product to approach the value one, the effective multiplication can become very large, causing current gain, I.sub..alpha.k, to increase, causing breakdown to occur.
As is known, the current level is affected by temperature and dV/dT. Increasing the temperature of a device increases the leakage current through it, and increasing dV/dT in the device increases the capacitive current therein. Thus, increases in temperature and dV/dT cause the current level in the device to increase, thereby decreasing the breakdown voltage of the device.
One of the operational problems that this dependence on temperature and dV/dT creates is that the breakdown voltage of the semiconductor power device is neither stable nor predictable. Users of such devices need to know the breakdown voltage of their devices with some certainty so that systems can be designed to achieve specific results. Another operational problem caused by this dependence is that changing breakdown voltage also causes the avalanche current capability of the device to become unstable and unpredictable.
Thus, the user of the device in an environment with changing temperature and dV/dT is faced with not only an unpredictable breakdown voltage, but also with a device having an unpredictably reduced capability. The term "ruggedness" is used herein to refer to the ability of a semiconductor power device to withstand temperature and dV/dT changes without inviting these problems.
Accordingly, it is an object of the present invention to provide a novel method and system for improving the ruggedness of a semiconductor power device.
It is a further object of the present invention to provide a novel apparatus and method in which ruggedness is improved by increasing the current through the wide base relative to the current through the emitter.
It is yet a further object of the present invention to provide a novel apparatus and method in which ruggedness is improved by diverting current from the emitter of the wide base transistor to the base.
It is still a further object of the present invention to provide a novel apparatus and method in which ruggedness is improved by injecting a current into the wide base at least as large as the current associated with temperature and dV/dT effects.
It is another object of the present invention to provide a novel apparatus and method in which a resistive current path connects the base of the wide base transistor of a semiconductor power device to the power terminal which forms the collector of the transistor.
It is still another object of the present invention to provide a novel system and method for improving the ruggedness of semiconductor power devices in which a grid of low resistivity semiconductor material is added to a buffer layer to improve lateral conductivity.
It is yet another object of the present invention to provide a novel system and method in which an external resistive path is provided for injecting a current into the base of a wide base transistor to reduce the dependence on temperature and dV/dT in a semiconductor power device.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of preferred embodiments.